Product Summary

The ZL50018 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048, 4.096, 8.192 or 16.384 Mbps. The ZL50018 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored. The applications of the ZL50018 include PBX and IP-PBX, Small and medium digital switching platforms, Wireless base stations and controllers, Remote access servers and concentrators, Multi service access platforms, Digital Loop Carriers, Computer Telephony Integration.

Parametrics

ZL50018 absolute maximum ratings: (1)I/O Supply Voltage VDD_IO: -0.5 to 5.0V; (2)Core Supply Voltage VDD_CORE: -0.5 to 2.5V; (3)Input Voltage VI_3V: -0.5 to VDD + 0.5V; (4)Input Voltage (5 V-tolerant inputs) VI_5V: -0.5 to 7.0V; (5)Continuous Current at Digital Outputs Io: 15mA; (6)Package Power Dissipation PD: 1.5W; (7)Storage Temperature TS: - 55 to +125℃.

Features

ZL50018 features: (1)2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or 16.384 Mbps; (2)32 serial TDM input, 32 serial TDM output streams; (3)Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 3 specifications; (4)Output clocks have less than 1 ns of jitter (except for the 1.544 MHz output); (5)DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs; (6)Programmable key DPLL parameters (filter corner frequency, locking range, auto-holdover hysteresis range, phase slope, lock detector range); (7)Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates); (8)Output streams can be configured as bidirectional for connection to backplanes; (9)Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and; (10)output data rates can differ; (11)Per-stream high impedance control outputs (STOHZ) for up to 16 output streams; (12)Per-stream input bit delay with flexible sampling point selection; (13)Per-stream output bit and fractional bit advancement; (14)Per-channel ITU-T G.711 PCM A-Law/?Law Translation; (15)Multiple frame pulse and reference clock output; (16)Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz; (17)Input frame pulses: 61 ns, 122 ns, 244 ns; (18)Per-channel constant or variable throughput delay for frame integrity and low latency applications; (19)Per Stream Bit Error Rate Test circuits; (20)Per-channel high impedance output control; (21)Per-channel message mode; (22)Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses; (23)Connection memory block programming; (24)Supports ST-BUS and GCI-Bus standards for input and output timing; (25)IEEE-1149.1 (JTAG) test port; (26)3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage.

Diagrams

ZL50018 block diagram

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ZL50018
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ZL50010
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ZL50011
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ZL50012
ZL50012

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ZL50012/GDC
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ZL50012/QCC
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ZL50012QCG1
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