(China (Mainland))
Product Summary
The IDT75P52100S100BX is a high performance pipelined low-power, synchronous full-ternary 32K x 72 entry device. Each entry location in the NSE has both a Data entry and an associated Mask entry. The IDT75P52100S100BX integrates content addressable memory (CAM) technology with high-performance logic. The IDT75P52100S100BX can perform Lookup and Learn NSE operations plus Read, Write, Burst Write, and Dual Write maintenance operations.
Parametrics
IDT75P52100S100BX absolute maximum ratings: (1) Organization: 128K x 36; (2) Speed: 100 MSPS; (3) Voltage: 1.8V; (4) I/O Voltage: 2.5/1.8V; (5) Interface – type: ASIC/FPGA.
Features
IDT75P52100S100BX features: (1)Full Ternary 32K x 72 bit content addressable memory; (2)Upgradeable to 64K x 72 and 128K x 72 NSEs; (3)Power Management; (4)Global Mask Registers; (5)Segments individually configurable; (6)36/72/144/288/576 multiple width lookups; (7)100M sustained lookups per second at 72 and 144 width lookups; (8)Burst write for high speed table updates; (9)Multi-match; (10)Learn new entries; (11)Dual bus interface; (12)Cascadable to 8 devices with no glue logic or latency penalty; (13)Glueless interface to standard ZBT. or Synchronous Pipelined Burst SRAMs; (14)Boundary Scan JTAG Interface (IEEE 1149.1compliant); (15)1.8V core power supply; (16)2.5V VBIAS power supply; (17)User selectable 2.5V or 1.8V I/O supply.
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