(China (Mainland))
Product Summary
The EPM7128SQC100-6 is a high-density, high-performance PLD. It is based on the second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7128SQC100-6 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
Parametrics
EPM7128SQC100-6 absolute maximum ratings: (1)VCC, Supply voltage: –2.0 to 7.0V when with respect to ground; (2)VI, DC input voltage: –2.0 to 7.0V; (3)IOUT, DC output current, per pin: –25 to 25mA; (4)TSTG, Storage temperature: –65 to 150 ℃ when No bias; (5)TAMB, Ambient temperature: –65 to 135 ℃ when under bias; (6)TJ, Junction temperature: max=150℃ when ceramic packages, under bias; max=135℃ when PQFP and RQFP packages, under bias.
Features
EPM7128SQC100-6 features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available.
Diagrams
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 EPM7128SQC100-6 |
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IC MAX 7000 CPLD 128 100-PQFP |
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EPM7128SQC100-6N |
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IC MAX 7000 CPLD 128 100-PQFP |
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