Product Summary

The CY7C1470V33-167AXI is a 3.3V 72-Mbit Synchronous pipelined burst SRAM with No Bus Latency (NoBL) logic, respectively. The CY7C1470V33-167AXI is designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33-167AXI is equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33-167AXI is pin compatible and functionally equivalent to ZBT device.

Parametrics

CY7C1470V33-167AXI absolute maximum ratings: (1)Storage Temperature:–65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage on VDD Relative to GND:–0.5V to +4.6V; (4)DC to Outputs in Tri-State:–0.5V to VDDQ + 0.5V; (5)DC Input Voltage:–0.5V to VDD + 0.5V; (6)Current into Outputs (LOW): 20mA; (7)Static Discharge Voltage: >2001V (per MIL-STD-883, Method 3015); (8)Latch-up Current: >200 mA.

Features

CY7C1470V33-167AXI features: (1)Pin-compatible and functionally equivalent to ZB; (2)Supports 250-MHz bus operations with zero wait states; (3)Available speed grades are 250, 200, and 167 MHz; (4)Internally self-timed output buffer control to eliminate the need to use asynchronous OE; (5)Fully registered (inputs and outputs) for pipelined operation; (6)Byte Write capability; (7)Single 3.3V power supply; (8)3.3V/2.5V I/O power supply; (9)Fast clock-to-output time; (10)3.0 ns (for 250-MHz device); (11)3.0 ns (for 200-MHz device); (12)3.4 ns (for 167-MHz device); (13)Clock Enable (CEN) pin to suspend operation; (14)Synchronous self-timed writes; (15)CY7C1470V33 and CY7C1472V33 available in lead-free 100 TQFP, and 165-ball fBGA packages. CY7C1474V33 available in 209-ball fBGA package; (16)IEEE 1149.1 JTAG Boundary Scan compatible; (17)Burst capability linear or interleaved burst order; (18)"ZZ" Sleep Mode option and Stop Clock option.

Diagrams

CY7C1470V33-167AXI block diagram

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