CY7C1315CV18-250BZC

Product Summary

The CY7C1315CV18-250BZC is a 1.8V Synchronous Pipelined SRAM, equipped with QDR.-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II read and write ports are completely independent of one another. In order to maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with four 36-bit words that burst sequentially into or out of the CY7C1315CV18-250BZC. Because data can be transferred into and out of the CY7C1315CV18-250BZC on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Parametrics

CY7C1315CV18-250BZC absolute maximum ratings: (1)Storage Temperature:–65℃ to +150℃; (2)Ambient Temperature with Power Applied:–10℃ to +85℃; (3)Supply Voltage on VDD Relative to GND:–0.5V to +2.9V; (4)Supply Voltage on VDDQ Relative to GND:–0.5V to +VDD; (5)DC Applied to Outputs in High-Z:–0.5V to VDDQ + 0.3V; (6)DC Input Voltage:–0.5V to VDD + 0.3V; (7)Current into Outputs (LOW): 20mA; (8)Static Discharge Voltage (MIL-STD-883, M. 3015): ＞2001V; (9)Latch-up Current: ＞200mA.

Features

CY7C1315CV18-250BZC features: (1)Separate independent read and write data ports; (2)Supports concurrent transactions; (3)300 MHz clock for high bandwidth; (4)4-word burst for reducing address bus frequency; (5)Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz; (6)Two input clocks (K and K) for precise DDR timing; (7)SRAM uses rising edges only; (8)Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches; (9)Echo clocks (CQ and CQ) simplify data capture in high speed systems; (10)Single multiplexed address input bus latches address inputs for both read and write ports; (11)Separate port selects for depth expansion; (12)Synchronous internally self-timed writes; (13)QDR.-II operates with 1.5 cycle read latency when the Delay Lock Loop (DLL) is enabled; (14)Operates as a QDR-I device with 1 cycle read latency in DLL off mode; (15)Available in x 8, x 9, x 18, and x 36 configurations; (16)Full data coherency, providing most current data; (17)Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD; (18)Available in 165-Ball FBGA package (13 x 15 x 1.4 mm); (19)Offered in both Pb-free and non Pb-free packages; (20)Variable drive HSTL output buffers; (21)JTAG 1149.1 compatible test access port; (22)Delay Lock Loop (DLL) for accurate data placement.

Diagrams