AD6652BBCZ

Product Summary

The AD6652BBCZ is a mixed-signal IF to baseband receiver consisting of dual 12-bit 65 MSPS ADCs and a wideband multimode digital downconverter (DDC). The AD6652BBCZ is designed to support communications applications where low cost, small size, and versatility are desired. The AD6652BBCZ is also suitable for other applications in imaging, medical ultrasound, instrumentation, and test equipment. The applications of the AD6652BBCZ include Communications, Diversity radio systems, Multimode digital receivers: GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE, IS95, IS136, CDMA2000, IMT-2000, I/Q demodulation systems, Smart antenna systems, General-purpose software radios, Broadband data applications, Instrumentation and test equipment.

Parametrics

AD6652BBCZ absolute maximum ratings: (1)AVDD Voltage: -0.3 V to +3.9 V; (2)VDD Voltage: -0.3 V to +2.75 V; (3)VDDIO Voltage: -0.3 V to +3.9 V; (4)AGND, DGND: -0.3 V to +0.3 V; (5)ADC VINA, VINB Analog Input Voltage: -0.3 V to AVDD + 0.3 V; (6)ADC Digital Input Voltage: -0.3 V to AVDD + 0.3 V; (7)ADC OTRA, OTRB Digital Output Voltage: -0.3 V to VDDIO + 0.3 V; (8)ADC VREF, REFA, REFB Input Voltage: -0.3 V to AVDD + 0.3 V; (9)DDC Digital Input Voltage: -0.3 V to VDDIO + 0.3 V; (10)DDC Digital Output Voltage: -0.3 V to VDDIO + 0.3 V; (11)Operating Temperature Range (Ambient): -40℃ to +85℃; (12)Maximum Junction Temperature Under Bias: 150℃; (13)Storage Temperature Range (Ambient): -65℃ to +150℃

Features

AD6652BBCZ features: (1)SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS); (2)Worst harmonic = 83dBc (to Nyquist @ 61.44 MSPS); (3)Integrated dual-channel ADC:; (4)Sample rates up to 65 MSPS; (5)IF sampling frequencies to 200 MHz; (6)Internal ADC voltage reference; (7)Integrated ADC sample-and-hold inputs; (8)Flexible analog input range (1 V to 2 V p-p); (9)Differential analog inputs; (10)ADC clock duty cycle stabilizer; (11)85 dB channel isolation/crosstalk; (12)Integrated wideband digital down converter (DDC):; (13)Crossbar switched DDC inputs; (14)Digital re-sampling for no integer decimation; (15)Programmable decimating FIR filters; (16)Flexible control for multicarrier and phased array; (17)Dual AGC stages for output level control; (18)Dual 16-bit parallel or 8-bit link output ports; (19)User-configurable built-in self-test (BIST) capability; (20)Energy-saving power-down modes.

Diagrams